1. Technical Field of the Invention
The present invention relates to the computer processing field and, in particular, to a method for reducing interrupt load in a multi-processor system. Such a multi-processor system can be implemented in, but not necessarily limited to, a Base Transceiver Station (BTS) in a mobile communications system.
2. Description of Related Art
In certain multi-processor applications, two (or more) Central Processor Units (CPUs) can communicate through use of a shared memory. For example, a BTS which has been developed by Ericsson for use in a Wideband Code Division Multiple Access (WCDMA) mobile communication system, includes a main processor board with two interoperable CPUs. These two CPUs can communicate with (e.g., send data to) each other through a shared memory unit. Nevertheless, the load on such a shared memory can be relatively high, and the number of interrupts needed for an operating system to process such inter-CPU communications can also be quite high.
For example, one common method used to communicate or convey data between two such CPUs is to employ a dual port First-In First-Out (FIFO) shared memory. With this method, the inter-CPU communication interrupts and associated data are processed sequentially (FIFO). However, a significant problem with the existing dual port FIFO memories is that they are quite expensive and relatively inefficient to use. Also, in certain applications (e.g., a Wideband BTS), with the exceedingly high load projected for inter-CPU communications in such applications, the use of dual port FIFO shared memories for such applications will not be feasible.
Another common method used to communicate or convey data between two such CPUs is to employ a shared memory area referred to as a mailbox. Using this method, the CPU sending data first writes the data into a mailbox area shared with the receiving CPU, and then transmits an interrupt for that CPU. Responsive to the interrupt from the sending CPU, the receiving CPU reads the stored data from the mailbox area. However, a significant problem with the existing mailbox approach used for inter-CPU communications is that the more data units (e.g., packets) being sent, the more times the receiving CPU will be interrupted. As such, the number of interrupts to be processed in this way can be exceedingly high.
A third common method used to communicate or convey data between two such CPUs is to employ two shared memory areas. Using this method, one memory area contains a ring buffer, and the other memory area contains two pointers. One pointer (referred to as an end pointer) is updated by the CPU which is sending data, and the second pointer (referred to as a start pointer) is updated by the receiving CPU. With this method, the receiving CPU can poll the end pointer for changes, or alternatively, the receiving CPU can be interrupted for each new data unit (e.g., packet) to be received (similar to the above-described mailbox method). Notably, a variation of this third method (i.e., increasing efficiency through buffer usage) is disclosed in U.S. Pat. No. 5,548,728 to Danknick.
In summary, the most significant problems associated with the use of the above-described (and other similar) inter-CPU communication methods is that the existing CPU load-consuming circuitry is not feasible for the high load applications to be implemented in the future (e.g., Wideband BTS inter-CPU communications). Also, for those applications being implemented in a real-time operational system (RTOS), their operations will be relatively inefficient if they are being interrupted a high percentage of time. For example, a projection for Wideband BTS applications is that 30% of the CPU capacity will be utilized for processing interrupts if the above-described inter-CPU communication methods are used. In any event, as described in detail below, the present invention successfully resolves the above-described and other related problems.
In accordance with a preferred embodiment of the present invention, a method for reducing interrupt load in a multi-processor system is provided, whereby two CPUs executing a real-time operating system can communicate with each other using a shared memory. A start pointer and end pointer are implemented in logic. By detecting a difference in the logic values for the two pointers, the receiving CPU will receive interrupts only when new data from the sending CPU has arrived in the shared memory and the shared memory was empty. Consequently, the operating system will not be disturbed with unnecessary interruptions, and the interrupt load will thus be low.
An important technical advantage of the present invention is that the CPU interrupt load can be significantly reduced, because a receiving CPU will be interrupted only when new data from the sending CPU has arrived in the shared memory area.
Another important technical advantage of the present invention is that a CPU does not have to be interrupted while a large amount of data is being transferred from another CPU.
Still another important technical advantage of the present invention is that a receiving CPU is not required to poll a shared memory location in order to find new data conveyed from another CPU.
Yet another important technical advantage of the present invention is that since a receiving CPU will be interrupted only when the load is relatively low, the overall CPU capacity will be increased for handling a relatively large amount of data using a shared memory.
Still another important technical advantage of the present invention is that since the real-time operating system will not be interrupted to a great extent, the operating system""s behavior will be more stable.
Still another important technical advantage of the present invention is that the pointers and method can be implemented in relatively inexpensive, uncomplicated logic.